Reducing Power in Multi-Core Network Processors through Data Filtering

We propose a data filtering method to reduce the power consumption of high-end processors with multiple execution cores. Although the proposed method can be applied to a wide variety of multi-processor systems including MPPs, SMPs and any type of single-chip multiprocessor, we concentrate on Network Processors, where most of the existing architectures use the multiple core design methodology. The proposed method uses an execution unit called Data Filtering Engine that processes data with low temporal locality before it is placed on the system bus. The execution cores use locality to decide which load instructions have low temporal locality and which portion of the surrounding code should be off-loaded to the data filtering engine. Control Interface(s) Our technique reduces the power consumption, because a) the low temporal data is not placed onto the bus, which is one of the most power consuming units in the processor, b) the L1 misses due to the low temporal data are prevented, and c) the conflict misses caused by low temporal data are also reduced resulting in even less accesses to the L2 cache. Specifically, we show that our technique reduces the bus accesses in representative applications by as much as 31% and 12% on average. Co-processors